Substrate for semiconductor device, manufacturing method thereof, semiconductor device, and frame main body

ABSTRACT

A lead frame comprises lead frame body having cut-away portions cut away from the side surfaces of the lead frame body, die pad for securing semiconductor chip, bonding electrodes surrounding the die pad, external electrodes for allowing the lead frame to be mounted, wiring for surface treatment extending on the lead frame body with its end being located at a portion of each of the side surfaces of the lead frame body, the portion being opposed the cut-away portions. The bonding electrode and the wiring for surface treatment as well as the external electrode and the wiring for surface treatment are electrically connected, respectively. Even when the lead frame is electrostatically charged by friction with a transfer unit, the semiconductor chip on the lead frame avoids the electrostatic damage.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates generally to a substrate forsemiconductor device, a manufacturing method thereof, a semiconductordevice, and a frame main body. More particularly, it relates to thesubstrate for semiconductor device and the like wherein an insulatingsubstrate body for mounting the semiconductor device has a cut-awayportion cut away from a side surface thereof and wiring for surfacetreatment extends on the insulating substrate body with an end thereofgathering in a portion of a side surface of the insulating substratebody, the portion being opposed the cut-away portion, thereby preventingthe wiring for surface treatment from extending through the side surfaceof the insulating substrate body so that even when the substrate getsstatic electricity during the transfer thereof, the semiconductor chipcan avoid an electrostatic damage.

[0003] 2. Description of Related Art

[0004] In recent years, there have been demands for higher speed anddownsizing of a semiconductor device. As semiconductor devices capableof meeting the higher speed and downsizing requirements, Land Grid Array(LGA), Ball Grid Array (BGA), and the like are known.

[0005] Out of these, the LGA is configured as shown in FIGS. 1 and 2.FIG. 1 is a sectional side elevation of the semiconductor device 1, andFIG. 2 shows a segment of a lead frame 10, which is a substrate forsemiconductor device used in the semiconductor device 1 as shown in FIG.1.

[0006] The lead frame 10 comprises a lead frame body 12, which is aninsulating substrate body. A die pad 12 a disposed on a top surface ofthe lead frame body 12 mounts a semiconductor chip 14, which is includedin the semiconductor device 1. Around the die pad portion 12 a, aplurality of bonding electrodes (lands) 16 is deposited and formed so asto surround it as shown in FIG. 2. Electrodes of the semiconductor chip14 connect the bonding electrodes 16 with gold wires 18 as shown inFIG. 1. The top surface side of the lead frame body 12 is molded(sealed) by a resin 20 so that the semiconductor chip 14, the gold wires18, and the bonding electrodes 16 are respectively covered thereby.

[0007] On the bottom surface of the lead frame body 12, externalelectrodes 22 for allowing the lead frame 10 to be mounted are depositedand formed. Each of the external electrodes 22 is electrically connectedto the bonding electrode 16. As is well known, the electrical conductionbetween the bonding electrodes 16 and the external electrodes 22 areaccomplished by through holes or the like.

[0008] Each of the surfaces of the bonding electrodes 16 and theexternal electrodes 22 is subjected to surface treatment forsatisfactorily ensuring bonding with the semiconductor chip 14 and jointwith soldering paste applied onto a substrate for mounting.

[0009] The surface treatment is generally plating treatment. The platingtreatment is carried out in the following manner. First, for example,the surface is subjected to nickel plating treatment for the undercoat,and then subjected to a gold plating treatment. As is well known, anelectroplating process is often used as the process for performing theplating treatment. As shown in FIGS. 1 and 2, both of the bondingelectrodes 16 and the external electrodes 22 have wiring for platingtreatment (wiring 24 for surface treatment), respectively. The wiring 24for surface treatment passes a current to carry out the electroplatingprocess.

[0010]FIG. 3 shows a frame main body 30 prior to cutting it into thelead frames 10 as use for semiconductor chips. The frame main body 30 isan insulating substrate having a size capable of providing several leadframes 10. All the wiring 24 for surface treatment extend on the framemain body 30 with the ends thereof being led through the opposite sidesurfaces 31 a and 31 b. Solder resist layer generally insulates theupper and lower opposite surfaces of the lead frame body 12 except foran area including the bonding electrodes 16. Namely, an area 32 and thedie pad 12 a which mounts the semiconductor chip 14, are insulated in acase shown in FIG. 2.

[0011] Herein, the cut ends of the wiring 24 for surface treatment areexposed from the side surfaces 31 a and 31 b of the frame main body 30.This is apparent from the configuration of FIG. 4.

[0012] As shown in FIG. 4, an original plate 40 for providing the leadframe main bodies 30 is an insulating substrate having a size capable offorming therein a plurality of frame main bodies 30. The original plate40 has secondary lines 26, which are the lines obtained by extending thewiring 24 for surface treatment, from the opposite side surfaces (theportions which will be the side surfaces 31 a, 31 b after cutting) ofeach of the frame main bodies 30. A large number of these secondarylines 26 are all connected to buses La and Lb wired at upper and lowersections, respectively, of the frame main body 30.

[0013] Then, the wiring 24 for surface treatment, secondary lines 26,and a pair of the buses La and Lb of the frame main body 30 arepatterned so that the buses La and Lb are led through openings 42, 42provided on the left and right side faces 41 a and 41 b of the originalplate 40. Further, connection terminals (electrode terminals) 43, 43 forthe buses La and Lb are deposited and formed on a portion of theoriginal plate 40 opposed the opening 42. The connection terminals 43,43 are the electrodes to be used for the plating treatment.

[0014] Then, applying prescribed voltage to the buses La and Lb whileimmersing the original plate 40 in a prescribed plating bath allows thebonding electrodes 16 and the external electrodes 22 to be subjected tothe plating treatment. After the plating treatment, the original plate40 is cut along the dot-dash lines shown in FIG. 4 to obtain a pluralityof the frame main bodies 30 shown in FIG. 3. Therefore, when theoriginal plate 40 is divided into the frame main bodies 30, the wiring24 for surface treatment and their respective secondary lines 26 areseparated from each other. The wiring 24 for surface treatment leadsthrough the opposite side surfaces 31 a and 31 b of the frame main body30. As the result thereof, the respective cut ends of the wiring 24 forsurface treatment are exposed from the opposite side surfaces 31 a and31 b of the frame main body 30.

[0015] Incidentally, after completion of division into frame main bodies30 as shown in FIG. 3, generally, no frame main body 30 is cut into leadframes (segments) each having a size corresponding to each semiconductorchip. Thus, the fixing of the semiconductor chip 14, wire bonding, andthe mold treatment by a resin are performed on the frame main body 30.The frame main body 30 is transferred to respective processing steps, orsubjected to a chucking process while remaining the same size as theframe main body 30.

[0016] During the transfer process and the chucking process, a transferunit and a chucking unit often come into contact with the insulatingsubstrate body, which is the lead frame body 12. Accordingly, when thelead frame body 12 is rubbed, a surface of the lead frame body 12 may beelectrostatically charged. If the surface of the lead frame body 12 iselectrostatically charged, discharge occurs when the surface of the leadframe body 12 moves closer to a metallic portion of the transfer unit orthe chucking unit. Discharge current at this step flows in thesemiconductor chip 14 via the wiring 24 for surface treatment.Alternatively, discharge occurs between the metallic portion of thetransfer unit or the chucking unit and the wiring 24 for surfacetreatment. In this case, discharge current flows into the semiconductorchip 14. By such a repetition of charging and discharging, thesemiconductor chip may be damaged by static electricity.

[0017] As the semiconductor devices having a high possibility of beingdamaged by static electricity, mention may be made of higher density-,and downsizing-oriented LGA, BGA, and the like. As described above, withthe semiconductor device involving higher speed of processing and higherdensity, the reduction in size of a single semiconductor element and thereduction in thickness of an oxide film with miniaturization in waferprocessing are remarkable. Therefore, such the semiconductor device issusceptible to static electricity. As a result, the semiconductorelement in the semiconductor device has a high possibility of undergoingelectrostatic damage (ESD damage) also due to slight charging anddischarging.

[0018] One object of the present invention is to improve a capacity foreffective protection against an electrostatic damage of the substratefor semiconductor device, the semiconductor device, and the like,respectively.

[0019] Another object of the invention is to provide a substrate forsemiconductor device, a semiconductor device, and the like, which arecapable of effectively preventing the electrostatic damage by achievingan electrically disconnected state.

[0020] A further object is to provide a manufacturing method formanufacturing the substrate for semiconductor device, which is capableof effectively preventing the semiconductor device from theelectrostatic damage.

SUMMARY OF THE INVENTION

[0021] According to the present invention, the foregoing objects areattained by a substrate for semiconductor device having insulatingsubstrate body. The insulating substrate body has cut-away portions cutaway from its side surfaces. Wiring for surface treatment extends on theinsulating substrate body and its ends are present on portions of eachof the side surfaces of the insulating substrate body, each portionbeing opposed the cut-away portion. The substrate for semiconductordevice further comprises die pad for securing semiconductor chip, aplurality of bonding electrodes, a plurality of external electrodes forallowing the substrate for semiconductor device to be mounted. The diepad is positioned on the insulating substrate body. The bondingelectrodes surround the die pad. Each of the external electrodes iselectrically connected to the bonding electrode and positioned under theinsulating substrate body. The bonding electrode and the wiring forsurface treatment as well as the external electrode and the wiring forsurface treatment are electrically connected, respectively.

[0022] Friction occurs due to the rubbing of the wiring for surfacetreatment to be used for surface treatment against a transfer block or achucking block. According to the prevent invention, in order to preventthe static electricity charged at this time from flowing current to thesemiconductor chip through the wiring for surface treatment, therespective ends of the wiring for surface treatment are present onportions of each of the side surfaces of the insulating substrate body,each portion being opposed the cut-away portion.

[0023] With this configuration, even if the end faces of the substratefor semiconductor device is electrostatically charged by friction withthe transfer unit or the chucking unit during transfer or duringchucking, no discharge current flows through the wiring for surfacetreatment because no end of the wiring for surface treatment comes intocontact with the transfer unit or the chucking unit. Therefore, even fora semiconductor chip of an LGA or BGA type, or the like, which tends toundergo electrostatic damage, it is possible to effectively protect thesemiconductor chip from damage by static electricity (electrostaticdamage).

[0024] In accordance with one aspect of the invention, wiring forsupplying power to the semiconductor chip and for grounding may beprovided. The wiring for supplying power to the semiconductor chip andfor grounding is located at a side surface of the insulating substratebody except for the cut-away portion. Alternatively, the wiring forsupplying power to the semiconductor chip and for grounding is locatedon both sides of the wiring for surface treatment. Namely, the wiringfor surface treatment is positioned between one wiring for supplyingpower to the semiconductor chip and for grounding and the other wiringfor supplying power to the semiconductor chip and for grounding.

[0025] According to this aspect of the invention, when the semiconductorchip of the above aspect is charged, discharge occurs from thesemiconductor chip via the wiring for power supply or grounding. As aresult, it is possible to prevent the semiconductor chip fromelectrostatic damage.

[0026] In accordance with another aspect of the invention, a substratefor semiconductor device comprises insulating substrate body having anopening therein, and wiring for surface treatment extending on theinsulating substrate body. The opening divides the wiring for surfacetreatment at midpoint.

[0027] According to the invention, the wiring for surface treatmentrefrains from acting as discharge paths of the static electricityincluding the semiconductor chip.

[0028] In accordance with further aspect of the invention, a method formanufacturing the above substrates for semiconductor device comprisescutting the wiring for surface treatment after performing the surfacetreatment on the bonding electrode and the external electrode using thewiring for surface treatment, and undergoing a mounting operation formounting the semiconductor chip after the cut processing.

[0029] In accordance with such the manufacturing method including thesteps of cutting the wiring for the surface treatment by slitting it, orthe like, after a surface treatment, ends of the wiring for surfacetreatment may be exposed at the side surfaces of the insulatingsubstrate body. Since, if so, the internal wiring for surface treatmentis electrically disconnected, no discharge current of static electricityflows through the semiconductor chip via the wiring for surfacetreatment. As a result, there is no risk that the semiconductor chipwill be damaged by static electricity.

[0030] In accordance with still further aspect of the invention, asubstrate for semiconductor device comprises insulating substrate bodyon which wiring for connecting a bonding electrode and an externalelectrode for allowing the substrate for semiconductor device to bemounted extends. Ends of the wiring for connecting the bonding electrodeand the external electrode are located at the inside from the sidesurfaces of the insulating substrate body. Die pad is positioned on theinsulating substrate body. A plurality of bonding electrodes surroundsthe die pad. Each external electrode is electrically connected to thebonding electrode and positioned under the insulating substrate body.

[0031] According to this aspect of the invention, the positions at whichthe wiring for connecting the bonding electrodes and the externalelectrodes respectively formed on upper and lower opposite sides of theinsulating substrate body is formed are restricted. Therefore, thewiring for connecting the bonding electrodes and the external electrodescannot extend to the side surfaces of the insulating substrate body. Inthis case, an electroless plating treatment as the surface treatment isperformed for the following reason. For the electroless platingtreatment, the wiring for surface treatment are not required, and hencethere is no necessity to extend the wiring for surface treatment to theside surfaces of the insulating substrate body.

[0032] In accordance with still another aspect of the invention, asemiconductor device comprises a substrate for semiconductor devicehaving insulating substrate body, a semiconductor chip secured on thesubstrate for semiconductor device, and sealing compound for sealing thesemiconductor chip. The substrate for semiconductor device provides abonding electrode on a side on which the semiconductor chip is mounted.The substrate for semiconductor device also provides an externalelectrode for allowing the substrate for semiconductor device to bemounted on the opposite side. The bonding electrode and the externalelectrode are provided with wiring for surface treatment. The wiring forsurface treatment extends on the insulating substrate body and its endsare located at a portion of each of the side surfaces of the insulatingsubstrate body, the portion being opposed cut-away portion cut away fromthe side surface of the insulating substrate body.

[0033] By doing as described above, it is possible to provide thesubstrate for semiconductor device resistant to electrostatic damage.Further, by using the substrate for a semiconductor device, it ispossible to provide a semiconductor device resistant to electrostaticdamage.

[0034] In accordance with still further aspect of the invention, framemain bodies comprising a plurality of substrates for semiconductordevice described above are provided. According to these frame mainbodies, it is possible to provide a substrate for semiconductor deviceresistant to electrostatic damage.

[0035] The conclusion unit of this specification particularly points outand distinctly claims the subject matter of the present invention. Thoseskill in the art, however, will best understand both the organizationand the method of operation of the invention, together with furtheradvantages and objects thereof, by reading the remaining portion of thespecification in view of the accompanying drawing(s) wherein likereference characters refer to like elements.

BRIEF DESCRIPTION OF THE DRAWING (S)

[0036]FIG. 1 is a cross sectional view of a semiconductor device using asemiconductor device in accordance with the related art;

[0037]FIG. 2 is a plan view of a substrate for semiconductor device ofthe related art;

[0038]FIG. 3 is a plan view showing a frame main body of the relatedart;

[0039]FIG. 4 is a plan view of an original plate for providing the framemain bodies of the related art;

[0040]FIG. 5 is a plan view of an essential part showing an embodimentof a substrate for semiconductor device in accordance with thisinvention;

[0041]FIG. 6 is a cross sectional view of a semiconductor device usingthe substrate for semiconductor device in accordance with thisinvention;

[0042]FIG. 7 is a plan view of a frame main body of the invention;

[0043]FIG. 8 is a plan view of an original plate of the invention forproviding the frame main bodies;

[0044]FIG. 9 is a plan view of an essential part showing anotherembodiment of the substrate for semiconductor device in accordance withthis invention;

[0045]FIG. 10 is a plan view of a frame main body of this anotherembodiment;

[0046]FIG. 11 is a plan view of an essential part showing a furtherembodiment of the substrate for semiconductor device in accordance withthis invention;

[0047]FIG. 12 is a plan view of a frame main body of this furtherembodiment;

[0048]FIG. 13 is a plan view of an essential portion showing a stillfurther embodiment of the substrate for semiconductor device inaccordance with this invention; and

[0049]FIG. 14 is a plan view of a frame main body of this still furtherembodiment.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT (S)

[0050] Subsequently, preferred embodiments of a substrate forsemiconductor device, a manufacturing method for manufacturing the same,a semiconductor device, and a frame main body in accordance with thisinvention will be described in detail by reference to the drawings.

[0051]FIG. 5 shows an embodiment of a lead frame 100 to be used as thesubstrate for semiconductor device in accordance with this invention.FIG. 6 is a cross sectional view of the semiconductor device 101 inaccordance with this invention using this lead frame 100. FIG. 7 shows aframe main body 103, which is to be segmented into each lead frame 100of FIG. 5.

[0052] A description will be given by reference to FIGS. 5 to 7.According to the embodiment of this invention, the lead frame 100comprises a lead frame body 112, which is insulating substrate body. Thelead frame 100 also comprises a die pad 112 a in rectangle form formounting and fixing a semiconductor chip 114 on the one surface (topsurface) of a lead frame body 112. A plurality of bonding electrodes 116is deposited and formed so as to surround the die pad 112 a. The numberof the bonding electrodes 116 to be formed differs according to thesizes of the semiconductor chip 114. In each example of the diagrams,the number of the bonding electrodes 116 is 16 (4×4) for convenience ofdescription.

[0053] On the other surface (bottom surface) of the lead frame body 112,a plurality of external electrodes 122 for allowing the lead frame 100to be mounted are deposited and formed so as to be in rectangle form.Each external electrode 122 is electrically connected to the bondingelectrode 116.

[0054] In this invention, not less than one cut-away portion is formedon each of opposite side surfaces 131 a and 131 b along the longer sidesof the lead frame body 112 constituting the lead frame 100. In theembodiment shown in FIG. 5, the lead frame body 112 has respective twocut-away portions 136, 136, 138, and 138 for each side surface, eachcut-away portion being cut away from the corresponding opposite sidesurface 131 a or 131 b. These two cut-away portions for each sidesurface are so set as to be at a prescribed distance from each other,for one die pad 112 a. Then, wiring 124 for surface treatment extends onthe lead frame body 112 and ends of the wiring 124 for surface treatmentare gathered at respective horizontal end faces (bottom portions) 136 a,136 a, 138 a, and 138 a of the side surfaces 131 a, 131 b of the leadframe body 112.

[0055] The wiring 124 for surface treatment is the wiring layers to beused for carrying out the surface treatment of the boding electrodes 116and the external electrodes 122 as described above. When the surfacetreatment is an electroplating process, the wiring is used as lead wiresfor applying a voltage for the plating treatment.

[0056] Therefore, as shown in FIG. 5, in this embodiment, the bondingelectrodes 116 disposed at four sections of upper, lower, left, andright sides are respectively divided into two equal groups per section.Thus, the wiring 124 for surface treatment in each group of fourindividually corresponding to a total of four bonding electrodes 116 iswired so as to be dispersed among their respective corresponding fourcut-away portions 136, 136, 138, and 138.

[0057] It is possible to set the depth, width, and the like of thecut-away portions 136, 136, 138, and 138 at given values, respectively.The depth and width of the cutaway portions 136, 136, 138 and 138 areselected in consideration of the sizes of the lead frame 100. They arealso selected so as not to be affected by the static electricitycharged.

[0058] Respective four cut-away portions 136, 136, 138, and 38 are cutaway from the corresponding opposite side surfaces 131 a and 131 b, asdescribed above so that the protrusion portions 140, 140 from the bottomportions 136 a and 136 a, 138 a and 138 a of the side surfaces 131 a,131 b of the lead frame body 112 remain. The protrusion portions 140,140 are used as chucking portions by a chucking unit. Whereas, for atransfer unit, the protrusion portions 140, 140 are mounted on thetransfer unit.

[0059] Gathering the wiring 124 for surface treatment in each of thebottom portions 136 a, 136 a, 138 a, and 138 a of the side surfaces 131a, 131 b of the lead frame body 112 opposed the plurality of the cutportions 136, 136, 138 and 138 in this manner, allows the ends of thewiring 124 for surface treatment and the transfer unit or the chuckingunit to avoid coming in direct contact with each other.

[0060] As a result, it is possible to provide the lead frame 100 and amanufacturing method thereof, which are capable of protecting thesemiconductor chip 114 from electrostatic damage with effectiveness andreliability. It is also possible to provide the semiconductor device 101resistant to the electrostatic damage.

[0061] When the semiconductor device 101 itself is transferred and/orchucked by the transfer unit and the chucking unit, respectively, andthe lead frame 100 is electrostatically charged by friction with theseunits, the charged surfaces are the protrusion portions 140, 140provided on the lead frame body 112. Since each of the protrusionportions 140, 140 and the wiring 124 for surface treatment arerelatively away from each other, there is a low possibility that thestatic electricity may be discharged through the wiring 124 for surfacetreatment as discharge paths. Further, even if the protrusion portions140, 140 are charged, the contact area with the transfer unit, thechucking unit, or the like is small, and very narrow, thereby resultingin a small amount of charge. As a result, even if the wiring 124 forsurface treatment acts as discharge paths, this conceivably has littleeffect on the semiconductor chip 114.

[0062] If the semiconductor chip 114 itself is charged, discharge occursupon the wire bonding by gold wires 18 when the wiring 124 for surfacetreatment is contacted to the metallic portions of the transfer unit orthe chucking unit. In a conventional configuration, the wiring 124 forsurface treatment and the like tend to come into contact with themetallic portion of the transfer unit or the like. As a result,discharge is more likely to occur. However, if the wiring 124 forsurface treatment is gathered in the bottom portions 136 a, 136 a, 138a, and 138 a of the side surfaces 131 a, 131 b of the lead frame body112 opposed the cut-away portions 136, 136, 138, and 138 according tothis invention, the wiring 124 for surface treatment becomes less likelyto come into contact with the metallic portion of the transfer unit orthe like. As a result, discharge becomes less likely to occur. Thisenables the semiconductor chip 114 to enhance its capacity forprotection against the electrostatic damage.

[0063] Further, the insulating components of the transfer unit, or theinsulating portions of the chucking unit may become electrostaticallycharged during operations of a semiconductor processing apparatus. Atthis step, discharge paths may be formed via the wiring 124 for surfacetreatment. In accordance with this embodiment, the probability offormation of the discharge paths by the wiring 124 for surface treatmentis very low also in this case.

[0064] This is because the cut ends of the wiring 124 for surfacetreatment are present on the bottom portions 136 a, 136 a, 138 a, and138 a of the side surfaces 131 a, 131 b of the lead frame body 112 cutmore inwardly from the protrusion portions 140, 140 and thus, the gapfor forming the discharge paths becomes wider than the conventional one.Thus, the probability of forming the discharge paths becomes very low.As a result, there is no possibility that the semiconductor chip 114 isdamaged by static electricity.

[0065] Incidentally, it is possible to form the frame main bodies 103 asconfigured in FIG. 7 by dividing the original plate 104 as shown in FIG.8. FIG. 8 shows the original plate 104, which is an insulating substratehaving a size capable of providing a plurality of the frame main bodies103. Openings 142 are provided at their respective prescribed positions(respective positions of the left and right opposite side surfaces 141a, 141 b in a case shown in FIG. 8). Buses La and Lb are wired so as toextend between the left and right openings 142, 142. Pairs of connectionterminals 143, 143 are respectively provided in a portion of theoriginal plate 104, the portion being opposed the opening 142.

[0066] The surface of the original plate 104 to be the frame main bodies103 is subjected to an insulation treatment by a solder resist exceptfor prescribed sections. Mutual connections between a plurality of thewiring 124 for surface treatment connected to their respective bondingelectrodes 116 formed on each frame main body 103 and the buses La andLb are established by secondary lines 126. The connections between theplurality of the wiring 124 for surface treatment connected to theirrespective external electrodes 122 and the buses La and Lb are alsoestablished by secondary lines 126.

[0067] In this drawing, there are shown only the secondary lines 126connected between the wiring 124 for surface treatment corresponding tothe bonding electrodes 116 and the buses La and Lb. The wiring 124 forsurface treatment is patterned so as to pass through the positions atwhich the cut-away portions 136, 136, 138, and 138 will be formed later,and connected to their respective corresponding secondary lines 126.

[0068] Subsequently, the original plate 104 is subjected to a platingtreatment. The plating treatment is an electroplating process. In thisembodiment, first, nickel plating is performed. Then, a gold platingtreatment is performed. Thereafter, the original plate 104 is cut alongdot-dash lines in the drawing, and divided into a plurality of the framemain bodies 103. Simultaneously upon division into the plurality of theframe main bodies 103, the cut-away portions 136, 136, 138, and 138 arealso formed.

[0069] After division into the frame main bodies 103, the bondingtreatment, the wire bonding treatment using the gold wires 118, and themold treatment of the semiconductor chip 114 are performed as with theconventional method. Then, the frame main body 103 is cut into leadframes 100 to manufacture the semiconductor device 101 as shown in FIG.6. According to this invention, it is possible to protect thesemiconductor chip from the electrostatic damage during such treatmentsteps with effectiveness. This enables the semiconductor device toenhance its capacity for protection against the electrostatic damage.

[0070] A description will be given to another embodiment of thesubstrate for semiconductor device in accordance with this invention.

[0071]FIGS. 9 and 10 show the embodiment wherein such a configuration isadopted that allows the static electricity charged on the semiconductorchip 114 shown in FIG. 6 which the lead frame 100 shown in FIG. 5mounts, to be discharged by utilizing wiring 244 for power supply(wiring for grounding) connected to the semiconductor chip 114. FIG. 9shows a lead frame 200. The lead frame 200 has lead frame body 212. Eachof the lead frames 200 is segmented from a frame main body 203 shown inFIG. 10.

[0072] As apparent from the embodiment shown in FIG. 9, the wiring 244for power supply or grounding is wired with respect to bondingelectrodes 217, 217 for power supply or grounding. The wiring 244 forpower supply or grounding has a little larger width than other wiring224 for surface treatment has. The wiring 244 for power supply orgrounding is used as power supply lines or grounding lines when thesemiconductor device 101 as shown in FIG. 6 is mounted. Such the wiring244 for power supply or grounding with a larger width allows theresistance to the electrostatic damage to be enhanced.

[0073] The wiring 244 for power supply or grounding extends on the leadframe body 212. Ends of the wiring 244 for power supply or grounding,however, are present on protrusion portions 240, 240 of the sidesurfaces of the lead frame body 212, i.e., the narrower protrusionportions 240 a, 240 a for each side surface in this example, not bottomportions 236 a, 236 a, 238 a, and 238 a of the side surfaces of the leadframe body 212 opposed the cut-away portions 236, 236, 238, and 238.

[0074] When extending the wiring 244 for power supply or groundingthrough the protrusion portions 240, 240 (the outermost side surfaces ofthe substrate), the cut ends of the wiring 244 for power supply orgrounding become more likely to come into contact with the metallicportion of the transfer unit or the chucking unit. Therefore, if thewiring 244 for power supply or grounding comes in contact with themetallic portion of the transfer unit or the like, the staticelectricity accumulated in the semiconductor chip 114 is discharged tothe side of the transfer unit or the chucking unit via the wiring 244for power supply or grounding. As a result, it is possible to preventthe semiconductor chip 114 from electrostatic damage.

[0075] Further, the wiring 244 for power supply or grounding is set atopposite sides of the wiring 224 for surface treatment provided atbottom portions 236 a, 236 a, 238 a, and 238 a of the side surfaces ofthe lead frame body 212 opposed the cut-away portions 236, 236, 238, and238. Namely, the wiring 224 for surface treatment is positioned betweenone wiring 244 for power supply or grounding and the other wiring 244for power supply or grounding. Therefore, in the segmentation process(dicing process of a semiconductor wafer) for manufacturing thesemiconductor device, metallic material such as a metallic mold foroutline processing first comes into contact with the wiring 244 forpower supply or grounding. This results in such a situation thatdischarge occurs via the wiring 244 for power supply or grounding. As aresult, it is possible to prevent the semiconductor chip 114 fromelectrostatic damage.

[0076] Additionally, FIGS. 11 and 12 show a further embodiment of thesubstrate for semiconductor device in accordance with this invention.FIG. 11 shows a lead frame 300, which is the substrate for semiconductordevice. The lead frame 300 has lead frame body 312, which is insulatingsubstrate body. Each of the lead frames 300 is segmented from a framemain body 303 shown in FIG. 12.

[0077] In this embodiment, the wiring 324 for surface treatment, whichhas been used for the surface treatment, is divided at its midpoint inplace of forming the above cut-away portions. For example, in thisembodiment, when the wiring 324 for surface treatment is dispersed intofour groups as shown in FIG. 11, four slits 350 are formed so as torespectively divide the wiring 324 for surface treatment at somemidpoints.

[0078] According to this configuration, the cut ends of the wiring 324for surface treatment are present on the outermost side surfaces 331 a,331 b of the lead frame body 312. Therefore, there is a high possibilitythat the cut ends may come into contact with the metallic portions ofthe transfer unit, or the like. However, each of the slits 350 dividesthe wiring 324 for surface treatment. Accordingly, even if the transferunit or the semiconductor chip is electrostatically charged, the wiring324 for surface treatment will not function as discharge paths via thesemiconductor chip. This allows the semiconductor chip to be protectedfrom electrostatic damage with effectiveness and reliability.

[0079] Incidentally, although not shown, the wiring for power supply andthe wiring for grounding in connection with the semiconductor chip arewired in a bypassing manner so as not to be divided by the slits 350.

[0080] Any of the embodiments described above shows the case where thewiring for surface treatment is formed on the insulating substrate.Then, in these cases, such a configuration has been devised that thewiring for surface treatment refrains from acting as discharge paths ofthe static electricity including the semiconductor chip.

[0081] Alternatively, as the surface treatments for the bondingelectrodes 116, 216, and 316 and the external electrodes of the leadframes 100, 200, and 300, an electroless plating process is conceivableother than the electroplating process as described above. For theelectroless plating process, the wiring for surface treatment for thebonding electrodes is unnecessary. Similarly, the wiring for surfacetreatment for the external electrodes is also unnecessary. In this case,only the wiring for connecting the bonding electrodes with the externalelectrodes is necessary.

[0082] Then, FIGS. 13 and 14 show a substrate for semiconductor devicewhen the surface treatment is performed according to the electrolessplating process, as a still further embodiment of this invention. FIG.13 shows a lead frame 400, which is the substrate for semiconductordevice in accordance with the invention. The lead frame 400 has leadframe body 412, which is insulating substrate body. Each of the leadframes 400 is segmented from a frame main body 403 shown in FIG. 14.

[0083] When the surface treatment of bonding electrodes 416 and theexternal electrodes of the lead frame 400 is performed according to theelectroless plating process, the cut-away portions 136, 136, 138, and138 as shown in FIG. 5 are not required to be formed. Thus, the leadframe body 412 of this embodiment, as shown in FIG. 13, has the sameplan configuration as the conventional one.

[0084] The wiring 454 for connection between the bonding electrodes 416and the external electrodes of the lead frame 400 is formed at least ona top surface of the lead frame body 412. The wiring 454 for connectionextends on the lead frame body 412 up to respective appropriate portionsthereof, not to the opposite side surfaces 431 a, 431 b of the leadframe body 412. Namely, ends of the wiring 454 for connection arelocated at the inside from the side surfaces 431 a, 431 b of the leadframe body 412. The connection between the ends and the externalelectrodes positioned under the lead frame 400 is established usingthrough holes 56 as shown in FIG. 13, or the like.

[0085] Since no wiring extends to the outermost side surfaces 431 a, 431b of the lead frame body 412 as the wiring 54 for connection, the wiring54 for connection cannot come into contact with the metallic portion ofthe transfer unit, the chucking unit, and the like. Accordingly, thewiring 54 for connection forms no discharge path via the semiconductorchip mounted on the lead frame 400. In consequence, this prevents thesemiconductor chip to be damaged by static electricity.

[0086] As described above, in accordance with the above embodiment ofthis invention, such a configuration is adopted that the ends of thewiring for surface treatment are gathered in portions of the sidesurfaces of the substrate for semiconductor device opposed therespective corresponding cut-away portions. Alternatively, such aconfiguration is adopted that the wiring for connection between theelectrodes disposed on the upper and lower opposite sides of thesubstrate for semiconductor device refrains extending to the side facesof the substrate for semiconductor device.

[0087] With these configurations, the transfer unit or the chucking unitcomes into no contact with the wiring for surface treatment or the otherwiring during transfer or during chucking. Therefore, even for thesemiconductor chip of LGA, BGA, or the like, which tends to undergoelectrostatic damage, it is possible to protect the semiconductor chipfrom electrostatic damage with effectiveness.

[0088] Further, in accordance with the manufacturing method of thisinvention, after carrying out the surface treatment, the wiring used forthe surface treatment is divided by cutting, slitting, or the like. Withthis configuration, even if the ends of the wiring for surface treatmentare exposed at the side surfaces of the substrate for semiconductordevice, the internal wiring for surface treatment is electricallydisconnected. Therefore, the electrostatic charge is not transferred tothe semiconductor chip via the wiring for surface treatment. As aresult, there is no risk that the semiconductor chip will be damaged bystatic electricity.

[0089] Thus, in accordance with this invention, it is possible toprovide a substrate for semiconductor device resistant to electrostaticdamage. Further, it is also possible to provide a semiconductor device,and a frame main body, which include such the substrate forsemiconductor device, resistant to electrostatic damage.

[0090] Therefore, this invention is preferably applicable to thesubstrate for semiconductor device of higher density- and higherspeed-oriented LGA, BGA, or the like.

[0091] While the foregoing specification has described preferredembodiments of the present invention, one skilled in the art may makemany modifications to the preferred embodiments without departing fromthe invention in its broader aspects. The appended claims therefore areintended to cover all such modifications as fall within the true scopeand spirit of the invention.

What is claimed is:
 1. A substrate for semiconductor device comprising: insulating substrate body having a cut-away portion cut away from a side surface thereof; die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body; wiring for surface treatment extending on said insulating substrate body with an end thereof being located at a portion of a side surface of said insulating substrate body, said portion being opposed said cut-away portion, wherein said bonding electrode and said wiring for surface treatment as well as said external electrode and said wiring for surface treatment are electrically connected, respectively.
 2. The substrate for semiconductor device as claimed in claim 1, wherein said insulating substrate body includes at least one cut-away portion on each of the opposite sides thereof.
 3. The substrate for semiconductor device as claimed in claim 1, wherein said insulating substrate body includes two cut-away portions on each of the opposite sides thereof; and wherein said insulating substrate body includes a chucking portion for allowing said insulating substrate body to be chucked, said chucking portion being formed between said two cut-away portions.
 4. The substrate for semiconductor device as claimed in claim 1, further comprising wiring for supplying power to said semiconductor chip and for grounding, wherein the wiring for supplying power to said semiconductor chip and for grounding is located at a side surface of said insulating substrate body except for said cut-away portion.
 5. The substrate for semiconductor device as claimed in claim 1, further comprising wiring for supplying power to said semiconductor chip and for grounding, wherein the wiring for supplying power to said semiconductor chip and for grounding is located on both sides of said wiring for surface treatment, said wiring for surface treatment being located at said portion of said side surface of said insulating substrate body, and said portion being opposed said cut-away portion, and wherein said wiring for surface treatment is positioned between one wiring for supplying power to said semiconductor chip and for grounding and the other wiring for supplying power to said semiconductor chip and for grounding.
 6. The substrate for semiconductor device as claimed in claim 1, wherein said wiring for supplying power to said semiconductor chip and for grounding has width wider than that said wiring for surface treatment has.
 7. The substrate for semiconductor device as claimed in claim 1, wherein said surface treatment is an electroplating process.
 8. A substrate for semiconductor device comprising: insulating substrate body having an opening therein; die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body; wiring for surface treatment extending on said insulating substrate body, wherein said opening divides said wiring for surface treatment at midpoint, and wherein said bonding electrode and said wiring for surface treatment as well as said external electrode and said wiring for surface treatment are electrically connected, respectively.
 9. The substrate for semiconductor device as claimed in claim 7, wherein said surface treatment is an electroplating process.
 10. A manufacturing method of manufacturing a substrate for semiconductor device, said substrate including insulating substrate body having a cut-away portion cut away from a side surface thereof, die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body, a plurality of bonding electrodes surrounding said die pad, a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body, and wiring for surface treatment provided for said bonding electrode and said external electrode, respectively, comprising the steps of: cutting said wiring for surface treatment after performing said surface treatment on said bonding electrode and said external electrode using said wiring for surface treatment; and undergoing a mounting operation for mounting said semiconductor chip after said cut processing.
 11. The manufacturing method as claimed in claim 10, wherein said surface treatment is an electroplating process.
 12. A substrate for semiconductor device comprising: insulating substrate body; die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body; and wiring for connection between said bonding electrode and said external electrode, wherein said wiring extends on said insulating substrate body with an end thereof being located at the inside from the side surface of said insulating substrate body.
 13. The insulating substrate for semiconductor device as claimed in claim 12, wherein said surface treatment for said bonding electrode and said external electrode is an electroless plating process.
 14. A semiconductor device comprising: a substrate for semiconductor device having insulating substrate body; a semiconductor chip secured on said substrate for semiconductor device; and sealing compound for sealing said semiconductor chip, wherein said substrate for semiconductor device provides a bonding electrode on a side on which said semiconductor chip is mounted, wherein said substrate for semiconductor device provides an external electrode for allowing said substrate for semiconductor device to be mounted on the opposite side, and wherein the bonding electrode and the external electrode are provided with wiring for surface treatment, said wiring for surface treatment extending on said insulating substrate body with an end thereof being located at a portion of a side surface of said insulating substrate body, said portion being opposed a cut-away portion cut away from said side surface of said insulating substrate body.
 15. A frame main body comprising a plurality of substrates for semiconductor device, each substrate for semiconductor device having a cut-away portion cut and including: die pad for securing semiconductor chip; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode; and wiring for surface treatment extending on said substrates for semiconductor device with an end thereof being located at a portion of a side surface of said frame main body, said portion being opposed said cut-away portion.
 16. The frame main body as claimed in claim 15, wherein said substrate for semiconductor device further including wiring for supplying power to said semiconductor chip and for grounding.
 17. A frame main body comprising a plurality of substrates for semiconductor device, each substrate for semiconductor device having an opening therein, and including: die pad for securing semiconductor chip; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode; and wiring for surface treatment extending on said substrates for semiconductor device, wherein said opening divides said wiring for surface treatment at midpoint.
 18. A frame main body comprising a plurality of substrates for semiconductor device, each substrate for semiconductor device including: die pad for securing semiconductor chip; a plurality of bonding electrodes surrounding said die pad; a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode; and wiring for connecting said bonding electrode and said external electrode extending on said substrate for semiconductor device with an end thereof being located at the inside from a side surface of said frame main body.
 19. An original plate for providing frame main bodies having openings, comprising a plurality of frame main bodies wherein bus for surface treatment for each frame main body extends between the openings. 